There are two major types of FET (Field-Effect Transistor) devices, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate and source and drain regions formed in a substrate. In MOSFETs, the control gate is formed above a thin dielectric insulator (gate dielectric) overlying a doped “channel” region between the source and drain regions. JFETs, like MOSFETs, have a doped channel region between their source and drain region but in JFETs, the control gate is formed by an oppositely doped gate region surrounding the channel region and forming a p-n junction therewith (hence the name “junction-gate” FET). In normal operation, this p-n junction is reverse biased. As the voltage applied to the control gate is varied, the electric field formed between the gate region and the channel region affects free carriers in the channel region to form a larger or smaller conduction channel through the channel region depending upon the applied gate voltage (the “field effect”). The gate voltage at which the conduction channel “pinches off” and becomes non-conductive is referred to as the “pinch off” voltage.
FET devices can be used as either amplifying or switching devices in electronic circuits. When used as an amplifying device, control of conduction between the source and drain through the channel region is used to amplify small AC signals. When used as a switching device (binary mode), a small current is used to switch the transistor between an “on” state and an “off” state. In a typical switching application, when the applied gate voltage causes a conduction channel to form, the FET device turns “on” and current can flow between the source and drain regions. Conversely, when the applied gate voltage causes the conduction channel to disappear or “pinch off”, the FET device turns “off” and current flow between the source and drain regions is blocked.
Modern computers, consumer electronics devices, and other computerized devices employ integrated circuit devices comprising many transistors operating in binary mode. In recent years, the computing power of computers and consumer electronic devices has increased dramatically. This has been accomplished by dramatic reductions in the size of transistor devices, resulting in a corresponding increase in the number of transistors on an integrated circuit device, in turn enabling reductions in the overall size of computer or consumer electronics devices, thereby increasing the amount of computing power that can be fit within a given volume. In addition, by increasing the number of transistors in an integrated circuit device, operational problems such as cross talk between physically adjacent conductors and signal propagation delays between different sections of a computing device can be reduced. As computers and consumer electronics continue to require increased computing power, there is considerable incentive for the semiconductor industry to continue the current trend towards increasingly compact and complex integrated circuits.
This trend toward more complex integrated circuits has been driven by increasing density of individual circuit elements on integrated circuit devices. Circuit elements such as metal oxide semiconductor field effect transistors (MOSFETs), resistors, etc. are typically used as components in an integrated circuit design. To increase the number of circuit elements within an integrated circuit, it is necessary to decrease the size of individual circuit elements. The size of individual circuit elements cannot be reduced arbitrarily. There are limitations to size reduction, including dimensional tolerance capabilities associated with manufacturing processes and various electrical phenomena that are associated with physical dimensions of circuit elements. In addition, the essential requirement for high reliability of integrated circuits itself places limitations on shrinking the size of such elements. The steps of identifying these and other limitations and discovering techniques for ameliorating these limitations have made possible the increasing complexity of integrated circuits.
As an example, the prior art in the field of manufacture, testing, and use of MOSFET devices has identified several problems that occur during long-term use of such devices. Of particular concern are various degradation or dynamic “wearout” mechanisms including, but not limited to, channel hot carrier (CHC) damage, negative bias temperature instability (NBTI) and Electromigration (EM).
NBTI in a MOSFET device is a serious detriment to the long-term stability of the MOSFET device. As explained in U.S. Pat. No. 6,521,469 to La Rosa et al., which is incorporated in its entirety by reference herein, NBTI results from charge buildup at the silicon—silicon oxide interface and is due to the influence of negative voltages on the gate electrode of MOS structures.
The simultaneous demands for higher drive current at lower operating voltages has led to more serious concerns over negative bias temperature instability (NBTI), which significantly shifts threshold voltage and reduces drive current. There are also indications that NBTI worsens exponentially with thinning gate oxide, and Vt (threshold voltage) shifts in the order of 50 mV are serious for devices operating at 1.2 V or below.
In order to produce accurate predictions of the expected service life and reliability of CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit technologies, it is essential to quantify the dynamic wearout mechanisms that can adversely affect the performance of the circuit elements (e.g., transistors, resistors) employed by those technologies. In SiO2 based CMOS technologies, Channel Hot Carrier (CHC) and NBTI damage have been identified as two key transistor-level FEOL (front end of line) wearout mechanisms that can reduce transistor lifetime. Typically these mechanisms are characterized under DC stress conditions and the effect of AC stressors is estimated based upon a “quasi-static” approximation.
Recent experimental data suggest that the quasi static approximation may not be accurate in the case of NBTI due to recovery effects. Evidently, there is a recovery effect that can occur whereby observable accelerated aging effects (e.g., threshold shift) due to applied AC “overstresses” can tend to reverse themselves over a period of time after the stress signals are removed. That is, the degradation (e.g., threshold shift) measured immediately after removing the stress will be greater than the degradation measured at some time later. Using conventional prior-art stress/characterization techniques, considerable time can elapse between stress and measurement, resulting in mischaracterization of the rate of degradation and inaccurate device lifetime predictions. This is particularly critical in High K technologies where the role of electron trapping in AC operation needs to be characterized.
Another problem with current accelerated aging techniques relates to the characterization of resistor/wire Electron Migration (EM) aging under AC condition. It can be expected that there will be an improvement of the End Of Life lifetime under AC stress conditions as compared to DC stress conditions. Currently, the difference between electro migration aging effects under DC and AC operating conditions is measured using external (to the chip) pulse generators to apply AC stress waveforms to the device under test (DUT). This approach is severely limited by the bandwidth of the cabling used for wafer level testing permitting DC vs. AC stress comparisons only at frequencies below 10 MHz.
There is thus a need in the art of reliability testing of MOSFET devices for improvement in the processes used to test for NBTI, which degrades the gate oxide of the MOSFET device, preferably without having to heat the full wafer on which the transistor is built. There is also a need for an NBTI test procedure that is sufficiently quick and cost-effective that the procedure can be applied to monitor NBTI on every lot in a semiconductor manufacturing line.
The current techniques used to characterize wearout have limitations that prevent a detailed characterization of both AC and DC wearout characteristics. Therefore, it is desirable to have a system and method that allows a better understanding, and capability for verifying experimentally, wearout mechanisms and their impacts on a given circuit design, to ensure continued high reliability for semiconductor devices and circuits.